Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centraliz...
Wedi'i Gadw mewn:
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| Awduron Eraill: | , |
| Fformat: | article |
| Iaith: | eng |
| Cyhoeddwyd: |
2018
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| Mynediad Ar-lein: | https://ieeexplore.ieee.org/document/8541463 http://repositorio.uti.edu.ec//handle/123456789/3446 |
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