Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA
This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques...
Furkejuvvon:
| Váldodahkki: | |
|---|---|
| Materiálatiipa: | article |
| Giella: | eng |
| Almmustuhtton: |
2010
|
| Fáttát: | |
| Liŋkkat: | http://bibdigital.epn.edu.ec/handle/15000/3706 |
| Fáddágilkorat: |
Lasit fáddágilkoriid
Eai fáddágilkorat, Lasit vuosttaš fáddágilkora!
|
Lasit fáddágilkoriid