Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA

This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques...

Fuld beskrivelse

Saved in:
Bibliografiske detaljer
Hovedforfatter: Cárdenas López, Daniel Felipe (author)
Format: article
Sprog:eng
Udgivet: 2010
Fag:
Online adgang:http://bibdigital.epn.edu.ec/handle/15000/3706
Tags: Tilføj Tag
Ingen Tags, Vær først til at tagge denne postø!