Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA
This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques...
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| Format: | article |
| Sprog: | eng |
| Udgivet: |
2010
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| Fag: | |
| Online adgang: | http://bibdigital.epn.edu.ec/handle/15000/3706 |
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