Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA
This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques...
Saved in:
| Main Author: | |
|---|---|
| Format: | article |
| Language: | eng |
| Published: |
2010
|
| Subjects: | |
| Online Access: | http://bibdigital.epn.edu.ec/handle/15000/3706 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Add Tag Be the first to leave a comment!