Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centraliz...
保存先:
| 第一著者: | |
|---|---|
| その他の著者: | , |
| フォーマット: | article |
| 言語: | eng |
| 出版事項: |
2018
|
| オンライン･アクセス: | https://ieeexplore.ieee.org/document/8541463 https://hdl.handle.net/20.500.14809/3446 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
タグ追加