Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centraliz...
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| Kolejni autorzy: | , |
| Format: | article |
| Język: | eng |
| Wydane: |
2018
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| Dostęp online: | https://ieeexplore.ieee.org/document/8541463 https://hdl.handle.net/20.500.14809/3446 |
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Dodaj etykietę | Streszczenie: | Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centralized configuration solution for a scalable multichip platform based on FPGA and PSoC devices is presented. For this purpose, a dedicated Master Device (MD) node has been used to configure a scalable network of Neuromorphic Devices (NDs). The NDs are general purpose devices which can be programmed to execute any neural algorithm based on spikes with a customized synapse topology. In the proposed approach, the communication channel is re-utilized and the Address Representation Event (AER) protocol modified to configure the entire system. This approximation allows achieving area and power consumption optimization since it eliminates the need to implement a specific instance per chip. Simulations shown demonstrate the performance and temporal characterization of this proposal. © 2018 IEEE. |
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