Axonal Delay Controller for Spiking Neural Networks Based on FPGA

In this paper, the implementation of a programmable Axonal Delay Controller (ADyC) mapped on a hardware Neural Processor (NP) FPGA-based is reported. It is possible to define axonal delays between 1 to 31 emulation cycles to global and local pre-synaptic spikes generated by NP, extending the tempora...

• 1. autor: Zapata, Mireya (author)
• Kolejni autorzy: Madrenas, Jordi (author), Alvarez, Jorge (author)
• Format: article
• Język: eng
• Wydane: 2020
• Dostęp online: https://link.springer.com/chapter/10.1007/978-3-030-20454-9_29; https://hdl.handle.net/20.500.14809/3428