Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centraliz...
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| Altres autors: | , |
| Format: | article |
| Idioma: | eng |
| Publicat: |
2018
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| Accés en línia: | https://ieeexplore.ieee.org/document/8541463 http://repositorio.uti.edu.ec//handle/123456789/3446 |
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