Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus

Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centraliz...

• Päätekijä: Zapata, Mireya (author)
• Muut tekijät: Jadán-Guerrero, Janio (author), Madrenas, Jordi (author)
• Aineistotyyppi: article
• Kieli: eng
• Julkaistu: 2018
• Linkit: https://ieeexplore.ieee.org/document/8541463; http://repositorio.uti.edu.ec//handle/123456789/3446